IBM said published technical results project that the new chip technology could deliver up to 50% higher performance or 70% better energy efficiency than its 2 nanometer node chips. The company pointed to generative AI, cloud infrastructure and next-generation electronics as potential areas that could benefit from the additional compute capacity.
“IBM’s latest chip breakthrough marks a landmark moment in computing, pushing technology beyond the nanometer era to the scale of atoms. With our new nanostack architecture, we’re not just making smaller transistors, we’re reinventing how chips are built to deliver dramatically more power and energy efficiency,” said Jay Gambetta, Director of IBM Research and IBM Fellow. “This industry-first innovation continues IBM’s legacy of leading in next-generation technologies and sets the foundation for the next era of computing.”
The central advance is IBM’s nanostack design, which vertically stacks and staggers transistors using 3D sequential integration. IBM said the approach allows more transistors to fit on a chip while also enabling different material combinations within stacked layers, giving chip designers more control over performance and power use.
IBM said the architecture has been experimentally validated through ultra-thin dielectric bonding in CMOS integration, dual-channel engineering capability and functional CMOS inverter operation with expected switching performance. The company said those results show that nanostack technology can be physically built and can support computation.
The company also highlighted new SRAM research presented at VLSI 2026. IBM said its nanostack architecture provides 40% SRAM scaling, which could help chip designers build more efficient processors while supporting the data bandwidth needs of advanced AI workloads.
While modern transistor node names no longer correspond directly to exact physical dimensions, IBM said its 0.7 nanometer technology shows that further scaling remains possible as the industry moves into angstrom-level design. The company said nanostack could support at least another decade of semiconductor scaling.
IBM said the work builds on its broader semiconductor research efforts, including its earlier 2 nanometer chip and ongoing work in silicon, AI hardware, logic and quantum processors. The research is being conducted with partners at a semiconductor research facility in Albany, New York, which is expected to house a High Numerical Aperture Extreme Ultraviolet lithography tool from ASML.
IBM is also working with partners including Lam Research, Tokyo Electron and SCREEN Semiconductor Solutions to develop High NA EUV processes and tools that have already produced working devices. The company said it sees the earliest adoption of nanostack technology at the sub-1 nanometer node, with a potential path to production in as early as the next five years.
This analysis is based on reporting from IBM.
Image courtesy of IBM.
This article was generated with AI assistance and reviewed for accuracy and quality.
